

------ clock divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity c1hz is
	port 	(clk : in std_logic;
			clkout : out std_logic;
			SWT  : in std_logic);
end c1hz;

architecture behavior of c1hz is
	constant num : integer := 4;
	signal cnt : integer := 0;
	begin
		process(clk, SWT)
			begin
				if(clk'event and clk='1' and SWT = '1') then
					if(cnt > (num/2 - 1))then
						clkout <= '1';
						cnt <= cnt+1;
						if(cnt = num-1)then
							cnt <= 0;
						end if;
					else
						cnt <= cnt+1;
						clkout <='0';
					end if;
				END if;
		end process;
end behavior;

----------LCD---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd is
	 port (clk : in std_logic;
			 SWT  : in std_logic;
			 ixin : in std_logic_vector(7 downto 0);
			 iyin : in std_logic_vector(7 downto 0);
			 
			 clkout: out std_logic_vector (2 downto 0);
			 ix   : out std_logic;
			 ixr   : out std_logic;
			 iy   : out std_logic;
			 iyr   : out std_logic);
end lcd;

architecture Behavioral of lcd is

	TYPE STATETYPE IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S1b, S2b, S3b, S4b, S5b, S6b);
	SIGNAL currstate, nextstate: statetype;

	constant Ycon : std_logic_vector(7 downto 0) := "11110000";
	constant Xcon : std_logic_vector(7 downto 0) := "10011111";

	
begin
state: PROCESS (currstate, SWT, ixin, iyin)
		BEGIN
			CASE currstate IS
				WHEN S0 =>
					IF (SWT = '1') THEN
						clkout(2) <= '0';
						clkout(1) <= '1';
						clkout(0) <= '1';
						
						iy <= '0';
						iyr <= '1';
						ix <= '0';
						ixr <= '1';

				
						nextstate <= S3b;	
					ELSE
						clkout(2) <= '0';
						clkout(1) <= '0';
						clkout(0) <= '0';
						
						iy <= '0';
						iyr <= '1';
						ix <= '0';
						ixr <= '1';
	
						
						nextstate <= S0;
					END IF;
					
				WHEN S1 =>
					clkout(2) <= '0';
					clkout(1) <= '0';
					clkout(0) <= '0';
				
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					
					if (iyin = Ycon) then
						nextstate <= S7;
					else
						nextstate <= S1b;
					end if;


				WHEN S2 =>	
					
					clkout(2) <= '0';
					clkout(1) <= '0';
					clkout(0) <= '1';	
									
					iy <= '0';
					iyr <= '0';
					ix <= '1';
					ixr <= '0';


					
					nextstate <= S2b;
					
					
				WHEN S3 =>
					
					clkout(2) <= '0';
					clkout(1) <= '1';
					clkout(0) <= '1';	
					
					iy <= '1';
					iyr <= '0';
					ix <= '0';
					ixr <= '1';

						
					nextstate <= S3b;
				WHEN S4 =>
				
					clkout(2) <= '1';
					clkout(1) <= '0';
					clkout(0) <= '0';	
					
					iy <= '0';
					iyr <= '1';
					ix <= '0';
					ixr <= '0';

					nextstate <= S4b;					
				
				WHEN S5 =>
					
					clkout(2) <= '1';
					clkout(1) <= '0';
					clkout(0) <= '1';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '1';
					ixr <= '0';

					nextstate <= S5b;
					
				WHEN S6 =>
					
					clkout(2) <= '1';
					clkout(1) <= '1';
					clkout(0) <= '1';	
					
					iy <= '1';
					iyr <= '0';
					ix <= '0';
					ixr <= '1';

					
					nextstate <= S6b;

				WHEN S7 =>
				
					clkout(2) <= '1';
					clkout(1) <= '0';
					clkout(0) <= '0';	
					
					iy <= '0';
					iyr <= '1';
					ix <= '0';
					ixr <= '0';
					
					nextstate <= S5;

				WHEN S8 =>
				
					clkout(2) <= '1';
					clkout(1) <= '0';
					clkout(0) <= '0';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					
					nextstate <= S1b;
					
				
					
---------------------------------------------------	
				WHEN S1b =>
					clkout(2) <= '0';
					clkout(1) <= '0';
					clkout(0) <= '0';
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					
					if (ixin = Xcon) then
						nextstate <= S3;
					else
						nextstate <= S2;
					end if;
					
				WHEN S2b =>	
				
					clkout(2) <= '0';
					clkout(1) <= '0';
					clkout(0) <= '1';
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					nextstate <= S1;
				


				WHEN S3b =>
					
					clkout(2) <= '0';
					clkout(1) <= '1';
					clkout(0) <= '1';
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';
	
					nextstate <= S1;
					
				WHEN S4b =>
				
					clkout(2) <= '1';
					clkout(1) <= '0';
					clkout(0) <= '0';
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					if (ixin = Xcon) then
						nextstate <= S6;
					else
						nextstate <= S5;
					end if;				

				WHEN S5b =>
					
					clkout(2) <= '1';
					clkout(1) <= '0';
					clkout(0) <= '1';
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					nextstate <= S4;

				WHEN S6b =>
					
					clkout(2) <= '1';
					clkout(1) <= '1';
					clkout(0) <= '1';
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					nextstate <= S8;
				
				
			END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				IF (SWT = '0') THEN
					currstate <= S0;
				ELSE
					currstate <= nextstate;
				END IF;
			END IF;
		END PROCESS statereg;
					
			
end Behavioral;




---------- Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_Counter IS
   PORT (clk : in std_logic;
         reset : IN std_logic;
         count : IN std_logic;
         counter : OUT std_logic_vector (7 downto 0));
END My_Counter;  

ARCHITECTURE behav OF My_Counter IS
	SIGNAL buff : std_logic_vector (7 downto 0) := "00000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "00000000";
			else
				if (count = '1') then
					buff <= buff + "00000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;


-----------3bit d flipflop------------------


library ieee ;
use ieee.std_logic_1164.all;
use work.all;

entity mydff is
	port(	clock   : 	in std_logic;
			data_in:	in std_logic_vector (2 downto 0);
			data_out:	out std_logic_vector (2 downto 0));
end mydff;

architecture behv of mydff is
begin

    process(data_in, clock)
    begin

        -- clock rising edge

	if (clock='1' and clock'event) then
	    data_out <= data_in;
	end if;

    end process;	

end behv;

---------Top level--------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity toplevel is
	port   (CLOCK_50	: in std_logic;
			SW   		: in STD_logic_vector (10 downto 0);
			LEDG		: out STD_logic_vector (3 downto 0);
			LEDR		: out STD_logic_vector (9 downto 2);
			GPIO_1		: inout STD_logic_vector (35 downto 0));
			
end toplevel;

Architecture struct of toplevel is

component lcd is
	 port (clk : in std_logic;
			 SWT  : in std_logic;
			 ixin : in std_logic_vector(7 downto 0);
			 iyin : in std_logic_vector(7 downto 0);
			 
			 clkout: out std_logic_vector (2 downto 0);
			 ix   : out std_logic;
			 ixr   : out std_logic;
			 iy   : out std_logic;
			 iyr   : out std_logic);
end component;

component c1hz is
	port 	(clk : in std_logic;
			clkout : out std_logic;
			SWT  : in std_logic);
end component;

component My_Counter IS
   PORT (clk : in std_logic;
         reset : IN std_logic;
         count : IN std_logic;
         counter : OUT std_logic_vector (7 downto 0));
END component;

component mydff is
	port(	clock   : 	in std_logic;
			data_in:	in std_logic_vector (2 downto 0);
			data_out:	out std_logic_vector (2 downto 0));
end component;

SIGNAL clk1, clk2, resetx, countx, resety, county: std_logic;
SIGNAL xval, yval: std_logic_vector(7 downto 0);
SIGNAL myclk, filtered_clk: std_logic_vector (2 downto 0);
begin
	clkdiv	: c1hz port map (CLOCK_50, clk1, SW(1));
	lcd_1 	: lcd port map (clk1, SW(0), xval, yval, myclk, countx, resetx, county, resety);
	xcount   : My_Counter port map (clk1, resetx, countx, xval);
	ycount   : My_Counter port map (clk1, resety, county, yval);
	filter   : mydff port map (CLOCK_50, myclk, filtered_clk);

	GPIO_1 (15) <= filtered_clk(0);
	GPIO_1 (19) <= filtered_clk(1);
	GPIO_1 (17) <= filtered_clk(2);
	GPIO_1 (21) <= sw(2);
	GPIO_1 (23) <= sw(3);
	GPIO_1 (25) <= sw(4);
	GPIO_1 (27) <= sw(5);
	GPIO_1 (29) <= sw(6);
	GPIO_1 (31) <= sw(7);
	GPIO_1 (33) <= sw(8);
	GPIO_1 (35) <= sw(9);
	

	GPIO_1 (13)	<= '0';

End struct;